As the degree of integration of semiconductor devices has increased, implanting ions by low energy, double ion implantation, and controlling the channeling effect by pre-amorphousness have been proposed for forming shallow source/drain junctions on a transistor. To apply such methods to forming shallow junctions under 0.1 μm, more research with regard to the physical and chemical characteristics of defects formed by ion implantation is needed.
Accordingly, instead of the conventional method of forming a source/drain junction in a semiconductor substrate, elevated source/drain junctions which are formed in an epitaxy layer grown on the surface of a semiconductor substrate have recently been proposed.
To clarify multiple layers and regions, the thickness of the layers are enlarged in the drawings. Wherever possible, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. As used in this patent, stating that any part (e.g., a layer, film, area, or plate) is in any way positioned on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, means that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween. Stating that any part is in contact with another part means that there is no intermediate part between the two parts.